1. Field of the Invention
This application relates to a semiconductor device and a fabrication method therefor.
2. Description of the Related Art
High integration of a semiconductor integrated circuit and an integrated circuit especially using an MOS transistor has been enhanced.
Miniaturization has been developed to a nano region of a Metal-Oxide-Semiconductor (MOS) transistor used in an integrated circuit with high integration of the semiconductor integrated circuit. When the miniaturization of the MOS transistor progressed, control of leakage current is difficult. Furthermore, there was a problem that it cannot make an occupation area of a circuit easily small in order to secure of needed amount of current value. In order to solve such a problem, it is proposed as Surrounding Gate Transistor (SGT) having a structure where a source, a gate, and a drain are disposed in a vertical direction for a substrate, and the gate surrounds a columnar semiconductor layer (for example, refer to Japanese Unexamined Patent Application H2-71556).